PIC18LF24K Datasheet, PDF (260/594 Pages) –

PIC18(L)F26/45/46K40
20.6.8
LEVEL TRIGGERED HARDWARE
LIMIT ONE-SHOT MODES
In Level Triggered One-Shot mode the timer count is
reset on the external signal level and starts counting
when the external signal level relinquishes the Reset.
Reset levels are selected as follows:
• High Reset level (MODE<4:0> = 01110)
• Low Reset level (MODE<4:0> = 01111)
When the timer count matches the PRx period count
then the timer is reset and the ON bit is cleared. When
the ON bit is cleared by either a PRx match or by soft-
ware control a new external signal edge is required
after the ON bit is set to start the counter.
When Level Triggered Reset One-Shot mode is used in
conjunction with the CCP PWM operation the PWM
drive goes active with the external signal edge that
starts the timer. The PWM drive goes inactive when the
timer count equals the CCPRx pulse-width count. The
PWM drive does not go active when the timer count
clears at the PRx period count match.
20.7 Timer2 Operation During Sleep
When TxPSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and PR2 registers will remain unchanged while
processor is in Sleep mode.
When TxPSYNC = 0, Timer2 will operate in Sleep as
long as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC, or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 260