PIC18LF24K Datasheet, PDF (141/594 Pages) –

PIC18(L)F26/45/46K40
11.3.3
READING THE DATA EEPROM
MEMORY
To read a data memory location, the user must write the
address to the NVMADRL and NVMADRH register
pair, clear NVMREG<1:0> control bit in NVMCON1
register to access Data EEPROM locations and then
set control bit, RD. The data is available on the very
next instruction cycle; therefore, the NVMDAT register
can be read by the next instruction. NVMDAT will hold
this value until another read operation, or until it is
written to by the user (during a write operation).
The basic process is shown in Example 11-5.
FIGURE 11-11:
PROGRAM FLASH
MEMORY READ
FLOWCHART
Start Read Operation
Select Memory:
Program Flash Memory, EEPROM,
Config. Words, User ID (NVMREG)
Select Word Address
(NVMADRH:NVMADRL)
Initiate Read Operation
(RD = 1)
Data read now in
NVMDAT
End Read Operation
11.3.4
WRITING TO THE DATA EEPROM
MEMORY
To write an EEPROM data location, the address must
first be written to the NVMADRL and NVMADRH
register pair and the data written to the NVMDAT
register. The sequence in Example 11-6 must be
followed to initiate the write cycle.
The write will not begin if NVM Unlock sequence,
described in Section 11.1.4 “NVM Unlock
Sequence”, is not exactly followed for each byte. It is
strongly recommended that interrupts be disabled
during this code segment.
Additionally, the WREN bit in NVMCON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, NVMCON1,
NVMADRL, NVMADRH and NVMDAT cannot be
modified. The WR bit will be inhibited from being set
unless the WREN bit is set. Both WR and WREN
cannot be set with the same instruction.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. A single Data
EEPROM word is written and the operation includes an
implicit erase cycle for that word (it is not necessary to
set FREE). CPU execution continues in parallel and at
the completion of the write cycle, the WR bit is cleared
in hardware and the NVM Interrupt Flag bit (NVMIF) is
set. The user can either enable this interrupt or poll this
bit. NVMIF must be cleared by software.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 141