PIC18LF24K Datasheet, PDF (438/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 31-9:
DIFFERENTIAL CVD WITH GUARD RING OUTPUT WAVEFORM
V_DD
V_SS
First Sample
Second Sample
Time
FIGURE 31-10: HARDWARE CVD SEQUENCE TIMING DIAGRAM
Precharge
Time
1-255 TINST
(TPRE)
Acquisition/
Sharing Time
1-255 TINST
(TACQ)
Conversion Time
(Traditional Timing of ADC Conversion)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
External and Internal External and Internal
Channels are
Channels share
Conversion starts
charged/discharged charge
Holding capacitor CHOLD is disconnected from analog input (typically 100 ns)
If ADPRE  0
If ADACQ 0
Set GO/DONE bit
If ADPRE = 0
If ADACQ = 0
(Traditional Operation Start)
31.4.5
ADDITIONAL SAMPLE AND HOLD
CAPACITANCE
Additional capacitance can be added in parallel with the
internal sample and hold capacitor (CHOLD) by using
the ADCAP register. This register selects a digitally
programmable capacitance which is added to the ADC
conversion bus, increasing the effective internal capac-
itance of the sample and hold capacitor in the ADC
module. This is used to improve the match between
internal and external capacitance for a better sensing
performance. The additional capacitance does not
affect analog performance of the ADC because it is not
connected during conversion. See Figure 31-11.
On the following cycle:
AADRES0H:AADRES0L is loaded,
ADIF bit is set,
GO/DONE bit is cleared
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 438