PIC18LF24K Datasheet, PDF (387/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 27-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
OERR
RCIDL
RXxPPS⁽¹⁾
RXx/DTx pin
PPS
Pin Buffer
and Control
Data
Recovery
MSb
Stop (8)
RSR Register
7 ••• 1
LSb
0 Start
Baud Rate Generator
BRG16
+1
SPxBRGH SPxBRGL
FOSC
÷n
Multiplier x4 x16 x64 ⁿ
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
FERR
Note 1: In Synchronous mode, the DT output and RX input PPS
selections should enable the same pin.
RX9
RX9D
RCxREG Register
FIFO
8
Data Bus
RCxIF
RCxIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 27-1,
Register 27-2 and Register 27-3, respectively.
The RXx/DTx and TXx/CKx input pins are selected with
the RXxPPS and TXxPPS registers, respectively. TXx,
CKx, and DTx output pins are selected with each pin’s
RxyPPS register. Since the RX input is coupled with the
DT output in Synchronous mode, it is the user’s
responsibility to select the same pin for both of these
functions when operating in Synchronous mode. The
EUSART control logic will control the data direction
drivers automatically.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 387