PIC18LF24K Datasheet, PDF (274/594 Pages) –

PIC18(L)F26/45/46K40
21.5.5 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to the CCPRxH:CCPRxL register pair. The
alignment of the 10-bit value is determined by the FMT
bit of the CCPxCON register (see Figure 21-5). The
CCPRxH:CCPRxL register pair can be written to at any
time; however the duty cycle value is not latched into
the 10-bit buffer until after a match between PR2 and
TMR2.
Equation 21-2 is used to calculate the PWM pulse
width.
Equation 21-3 is used to calculate the PWM duty cycle
ratio.
FIGURE 21-5:
PWM 10-BIT ALIGNMENT
CCPRxH
76543210
CCPRxL
76543210
Rev. 10-000 160A
12/9/201 3
FMT = 0
FMT = 1
CCPRxH
76543210
CCPRxL
76543210
10-bit Duty Cycle
9876543210
21.5.6 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 21-4.
EQUATION 21-4: PWM RESOLUTION
Resolution = ^{l--o---g----}--4---l-^_{o--P-g---R-}--2-²---_--+-----1----^--^ bits
Note:
If the pulse-width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
EQUATION 21-2: PULSE WIDTH
Pulse Width = CCPRxH:CCPRxL register pair 
TOSC  (TMR2 Prescale Value)
EQUATION 21-3: DUTY CYCLE RATIO
Duty Cycle Ratio = ^---C----C----P----R---x---H----:--4C---_-C--P--P--R--R--₂--x--L+-----r-1--e-_-g---i--s--t--e---r---p---a---i--r---^
CCPRxH:CCPRxL register pair are used to double
buffer the PWM duty cycle. This double buffering is
essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the
CCPRxH:CCPRxL register pair, then the CCPx pin is
cleared (see Figure 21-4).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 274