PIC18LF24K Datasheet, PDF (253/594 Pages) –

PIC18(L)F26/45/46K40
20.6.2 HARDWARE GATE MODE
The Hardware Gate modes operate the same as the
Software Gate mode except the TMRx_ers external
signal can also gate the timer. When used with the CCP
the gating extends the PWM period. If the timer is
stopped when the PWM output is high then the duty
cycle is also extended.
When MODE<4:0> = 00001 then the timer is stopped
when the external signal is high. When
MODE<4:0> = 00010, the timer is stopped when the
external signal is low.
Figure 20-5 illustrates the Hardware Gating mode for
MODE<4:0> = 00001 in which a high input level stops
the counter.
FIGURE 20-5:
HARDWARE GATE MODE TIMING DIAGRAM
MODE
0b00001
TMRx_clk
TMRx_ers
PRx
5
TMRx
0
1234501
2
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Rev. 10-000 196B
5/30/201 4
34501
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 253