PIC18LF24K Datasheet, PDF (264/594 Pages) –

PIC18(L)F26/45/46K40
21.2 Register Definitions: CCP Control
Long bit name prefixes for the CCP peripherals are
shown in Table 21-2. Refer to Section 1.4.2.2 “Long
Bit Names” for more information.
TABLE 21-2:
Peripheral
Bit Name Prefix
CCP1
CCP2
CCP1
CCP2
REGISTER 21-1: CCPxCON: CCPx CONTROL REGISTER
R/W-0/0
U-0
R-x
R/W-0/0
R/W-0/0
EN
—
OUT
FMT
bit 7
R/W-0/0
R/W-0/0
MODE<3:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EN: CCP Module Enable bit
1 = CCP is enabled
0 = CCP is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: CCPx Output Data bit (read-only)
bit 4
FMT: CCPW (pulse-width) Alignment bit
MODE = Capture mode:
Unused
MODE = Compare mode:
Unused
MODE = PWM mode:
1 = Left-aligned format
0 = Right-aligned format
Note 1: The set and clear operations of the Compare mode are reset by setting MODE = 4’b0000 or EN = 0.
2: When MODE = 0001 or 1011, then the timer associated with the CCP module is cleared. TMR1 is the
default selection for the CCP module, so it is used for indication purpose only.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 264