PIC18LF24K Datasheet, PDF (168/594 Pages) –

PIC18(L)F26/45/46K40
14.4 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable and priority
bits.
14.5 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are eight Peripheral Interrupt
Request Flag registers (PIR0, PIR1, PIR2, PIR3, PIR4,
PIR5, PIR6 and PIR7).
14.6 PIE Registers
The PIE registers contain the individual enable bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are eight Peripheral Interrupt
Enable registers (PIE0, PIE1, PIE2, PIE3, PIE4, PIE5,
PIE6 and PIE7). When IPEN = 0, the PEIE/GIEL bit must
be set to enable any of these peripheral interrupts.
14.7 IPR Registers
The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are eight Peripheral Interrupt
Priority registers (IPR0, IPR1, IPR2, IPR3, IPR4 and
IPR5, IPR6 and IPR7). Using the priority bits requires that
the Interrupt Priority Enable (IPEN) bit be set.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 168