PIC18LF24K Datasheet, PDF (255/594 Pages) –

PIC18(L)F26/45/46K40
20.6.4
LEVEL-TRIGGERED HARDWARE
LIMIT MODE
In the Level-Triggered Hardware Limit Timer modes the
counter is reset by high or low levels of the external sig-
nal TMRx_ers, as shown in Figure 20-7. Selecting
MODE<4:0> = 00110 will cause the timer to reset on a
low
level
external
signal.
Selecting
MODE<4:0> = 00111 will cause the timer to reset on a
high level external signal. In the example, the counter is
reset while TMRx_ers = 1. ON is controlled by BSF and
BCF instructions. When ON = 0 the external signal is
ignored.
When the CCP uses the timer as the PWM time base
then an external signal Reset will set the PWM output
high after a two clock synchronization delay or the timer
matches the PRx period value. The PWM output will
remain high until the external signal is released and the
timer counts up to match the CCPRx pulse-width value.
FIGURE 20-7:
LEVEL-TRIGGERED HARDWARE LIMIT TIMING DIAGRAM
Rev. 10-000198B
5/30/2014
MODE
0b00111
TMRx_clk
PRx
Instruction⁽¹⁾
BSF
5
BCF
BSF
ON
TMRx_ers
TMRx 0
TMRx_postscaled
12
0
123
4
50
0
123450
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 255