PIC18LF24K Datasheet, PDF (437/594 Pages) –

PIC18(L)F26/45/46K40
31.4.2 PRECHARGE CONTROL
The Precharge stage is an optional period of time that
brings the external channel and internal sample and
hold capacitor to known voltage levels. Precharge is
enabled by writing a non-zero value to the ADPRE
register. This stage is initiated when an ADC
conversion begins, either from setting the ADGO bit, a
special event trigger, or a conversion restart from the
computation functionality. If the ADPRE register is
cleared when an ADC conversion begins, this stage is
skipped.
During the precharge time, CHOLD is disconnected from
the outer portion of the sample path that leads to the
external capacitive sensor and is connected to either
VDD or VSS, depending on the value of the ADPPOL bit
of ADCON1. At the same time, the port pin logic of the
selected analog channel is overridden to drive a digital
high or low out, in order to precharge the outer portion
of the ADC’s sample path, which includes the external
sensor. The output polarity of this override is also deter-
mined by the ADPPOL bit of ADCON1. The amount of
time that this charging needs is controlled by the
ADPRE register.
Note:
The external charging overrides the TRIS
setting of the respective I/O pin. If there is
a device attached to this pin, Precharge
should not be used.
31.4.3 ACQUISITION CONTROL
The Acquisition stage is an optional time for the voltage
on the internal sample and hold capacitor to charge or
discharge from the selected analog channel.This
acquisition time is controlled by the ADACQ register. If
ADPRE = 0, acquisition starts at the beginning of
conversion. When ADPRE = 1, the acquisition stage
begins when precharge ends.
At the start of the acquisition stage, the port pin logic of
the selected analog channel is overridden to turn off the
digital high/low output drivers so they do not affect the
final result of the charge averaging. Also, the selected
ADC channel is connected to CHOLD. This allows
charge averaging to proceed between the precharged
channel and the CHOLD capacitor.
Note:
When ADPRE! = 0, acquisition time can-
not be ‘0’. In this case, setting ADACQ to
‘0’ will set a maximum acquisition time
(256 ADC clock cycles). When precharge
is disabled, setting ADACQ to ‘0’ will dis-
able hardware acquisition time control.
31.4.4 GUARD RING OUTPUTS
Figure 31-8 shows a typical guard ring circuit. CGUARD
represents the capacitance of the guard ring trace
placed on the PCB board. The user selects values for
RA and RB that will create a voltage profile on CGUARD,
which will match the selected acquisition channel.
The purpose of the guard ring is to generate a signal in
phase with the CVD sensing signal to minimize the
effects of the parasitic capacitance on sensing elec-
trodes. It also can be used as a mutual drive for mutual
capacitive sensing. For more information about active
guard and mutual drive, see Application Note AN1478,
“mTouch^TM Sensing Solution Acquisition Methods
Capacitive Voltage Divider” (DS01478).
The ADC has two guard ring drive outputs, ADGRDA
and ADGRDB. These outputs can be routed through
PPS controls to I/O pins (see Section
17.0 “Peripheral Pin Select (PPS) Module” for
details) and the polarity of these outputs are controlled
by the ADGPOL and ADIPEN bits of ADCON1.
At the start of the first precharge stage, both outputs
are set to match the ADGPOL bit of ADCON1. Once
the acquisition stage begins, ADGRDA changes
polarity, while ADGRDB remains unchanged. When
performing a double sample conversion, setting the
ADIPEN bit of ADCON1 causes both guard ring
outputs to transition to the opposite polarity of
ADGPOL at the start of the second precharge stage,
and ADGRDA toggles again for the second acquisition.
For more information on the timing of the guard ring
output, refer to Figure 31-8 and Figure 31-9.
FIGURE 31-8:
GUARD RING CIRCUIT
ADGRDA
RA
ADGRDB
RB
CGUARD
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 437