PIC18LF24K Datasheet, PDF (47/594 Pages) –

PIC18(L)F26/45/46K40
4.3.2.6 Oscillator Status and Manual Enable
The Ready status of each oscillator (including the
ADCRC oscillator) is displayed in OSCSTAT
(Register 4-4). The oscillators (but not the PLL) may be
explicitly enabled through OSCEN (Register 4-7).
4.3.2.7 HFOR and MFOR Bits
The HFOR and MFOR bits indicate that the HFINTOSC
and MFINTOSC is ready. These clocks are always
valid for use at all times, but only accurate after they are
ready.
When a new value is loaded into the OSCFRQ register,
the HFOR and MFOR bits will clear, and set again
when the oscillator is ready. During pending OSCFRQ
changes the MFINTOSC clock will stall at a high or a
low state, until the HFINTOSC resumes operation.
4.4 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the New Oscillator Source (NOSC) bits of the
OSCCON1 register. The following clock sources can be
selected using the following:
• External oscillator
• Internal Oscillator Block (INTOSC)
Note:
The Clock Switch Enable bit in
Configuration Word 1 can be used to
enable or disable the clock switching
capability. When cleared, the NOSC and
NDIV bits cannot be changed by user
software. When set, writing to NOSC and
NDIV is allowed and would switch the
clock frequency.
4.4.1
NEW OSCILLATOR SOURCE
(NOSC) AND NEW DIVIDER
SELECTION REQUEST (NDIV) BITS
The New Oscillator Source (NOSC) and New Divider
Selection Request (NDIV) bits of the OSCCON1
register select the system clock source and frequency
that are used for the CPU and peripherals.
When new values of NOSC and NDIV are written to
OSCCON1, the current oscillator selection will
continue to operate while waiting for the new clock
source to indicate that it is stable and ready. In some
cases, the newly requested source may already be in
use, and is ready immediately. In the case of a
divider-only change, the new and old sources are the
same, so the old source will be ready immediately. The
device may enter Sleep while waiting for the switch as
described in Section 4.4.3 “Clock Switch and
Sleep”.
When the new oscillator is ready, the New Oscillator
Ready (NOSCR) bit of OSCCON3 is set and also the
Clock Switch Interrupt Flag (CSWIF) bit of PIR1 sets. If
Clock Switch Interrupts are enabled (CSWIE = 1), an
interrupt will be generated at that time. The Oscillator
Ready (ORDY) bit of OSCCON3 can also be polled to
determine when the oscillator is ready in lieu of an
interrupt.
Note: The CSWIF interrupt will not wake the
system from Sleep.
If the Clock Switch Hold (CSWHOLD) bit of OSCCON3
is clear, the oscillator switch will occur when the New
Oscillator is Ready bit (NOSCR) is set, and the
interrupt (if enabled) will be serviced at the new
oscillator setting.
If CSWHOLD is set, the oscillator switch is suspended,
while execution continues using the current (old) clock
source. When the NOSCR bit is set, software should:
• Set CSWHOLD = 0 so the switch can complete,
or
• Copy COSC into NOSC to abandon the switch.
If DOZE is in effect, the switch occurs on the next clock
cycle, whether or not the CPU is operating during that
cycle.
Changing the clock post-divider without changing the
clock source (i.e., changing FOSC from 1 MHz to
2 MHz) is handled in the same manner as a clock
source change, as described previously. The clock
source will already be active, so the switch is relatively
quick. CSWHOLD must be clear (CSWHOLD = 0) for
the switch to complete.
The current COSC and CDIV are indicated in the
OSCCON2 register up to the moment when the switch
actually occurs, at which time OSCCON2 is updated
and ORDY is set. NOSCR is cleared by hardware to
indicate that the switch is complete.
4.4.2 PLL INPUT SWITCH
Switching between the PLL and any non-PLL source is
managed as described above. The input to the PLL is
established when NOSC selects the PLL, and
maintained by the COSC setting.
When NOSC and COSC select the PLL with different
input sources, the system continues to run using the
COSC setting, and the new source is enabled per
NOSC. When the new oscillator is ready (and
CSWHOLD = 0), system operation is suspended while
the PLL input is switched and the PLL acquires lock.
This provides a truly glitch-free clock switch operation.
Note: If the PLL fails to lock, the FSCM will
trigger.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 47