PIC18LF24K Datasheet, PDF (55/594 Pages) –

PIC18(L)F26/45/46K40
5.1 Clock Source
The input to the reference clock output can be selected
using the CLKRCLK register.
5.1.1 CLOCK SYNCHRONIZATION
Once the reference clock enable (EN) is set, the mod-
ule is ensured to be glitch-free at start-up.
When the reference clock output is disabled, the output
signal will be disabled immediately.
Clock dividers and clock duty cycles can be changed
while the module is enabled, but glitches may occur on
the output. To avoid possible glitches, clock dividers
and clock duty cycles should be changed only when the
CLKREN is clear.
5.2 Programmable Clock Divider
The module takes the clock input and divides it based
on the value of the DIV<2:0> bits of the CLKRCON reg-
ister (Register 5-1).
The following configurations can be made based on the
DIV<2:0> bits:
• Base FOSC value
• FOSC divided by 2
• FOSC divided by 4
• FOSC divided by 8
• FOSC divided by 16
• FOSC divided by 32
• FOSC divided by 64
• FOSC divided by 128
The clock divider values can be changed while the
module is enabled; however, in order to prevent
glitches on the output, the DIV<2:0> bits should only be
changed when the module is disabled (EN = 0).
5.3 Selectable Duty Cycle
The DC<1:0> bits of the CLKRCON register can be
used to modify the duty cycle of the output clock. A duty
cycle of 25%, 50%, or 75% can be selected for all clock
rates, with the exception of the undivided base FOSC
value.
The duty cycle can be changed while the module is
enabled; however, in order to prevent glitches on the
output, the DC<1:0> bits should only be changed when
the module is disabled (EN = 0).
Note: The DC1 bit is reset to ‘1’. This makes the
default duty cycle 50% and not 0%.
5.4 Operation in Sleep Mode
The reference clock output module clock is based on
the system clock. When the device goes to Sleep, the
module outputs will remain in their current state. This
will have a direct effect on peripherals using the
reference clock output as an input signal. No change
should occur in the module from entering or exiting
from Sleep.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 55