PIC18LF24K Datasheet, PDF (448/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 31-6: ADCLK: ADC CLOCK SELECTION REGISTER
U-0
—
bit 7
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
ADCS<5:0>
R/W-0/0
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
ADCS<5:0>: ADC Conversion Clock Select bits
111111 = FOSC/128
111110 = FOSC/126
111101 = FOSC/124



000000 = FOSC/2
REGISTER 31-7: ADREF: ADC REFERENCE SELECTION REGISTER
U-0
—
bit 7
U-0
U-0
R/W-0/0
U-0
U-0
—
—
ADNREF
—
—
R/W-0/0
R/W-0/0
ADPREF<1:0>
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
bit 4
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
ADNREF: ADC Negative Voltage Reference Selection bit
1 = VREF- is connected to external VREF-
0 = VREF- is connected to AVSS
Unimplemented: Read as ‘0’
ADPREF: ADC Positive Voltage Reference Selection bits
11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module
10 = VREF+ is connected to external VREF+
01 = Reserved
00 = VREF+ is connected to VDD
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 448