PIC18LF24K Datasheet, PDF (123/594 Pages) –

PIC18(L)F26/45/46K40
11.0 NONVOLATILE MEMORY
(NVM) CONTROL
Nonvolatile Memory (NVM) is separated into two types:
Program Flash Memory (PFM) and Data EEPROM
Memory.
PFM, Data EEPROM, User IDs and Configuration bits
can all be accessed using the NVMREG<1:0> bits of
the NVMCON1 register.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the operating
voltage range of the device.
NVM can be protected in two ways, by either code
protection or write protection. Code protection (CP and
CPD bits in Configuration Word 5L) disables access,
reading and writing to both PFM and Data EEPROM
Memory via external device programmers. Code
protection does not affect the self-write and erase
functionality. Code protection can only be reset by a
device programmer performing a Bulk Erase to the
device, clearing all nonvolatile memory, Configuration
bits and User IDs.
Write protection prohibits self-write and erase to a
portion or all of the PFM, as defined by the WRT bits of
Configuration Word 4H. Write protection does not affect
a device programmer’s ability to read, write or erase
the device.
TABLE 11-1: NVM ORGANIZATION AND ACCESS INFORMATION
Memory
PC<20:0>
ICSP™ Addr<21:0>
TBLPTR<21:0>
NVMADDR<9:0>
Execution
CPU
Execution
NVMREG
User Access
TABLAT NVMDAT
User Flash Memory
(PFM)
User IDs⁽²⁾
Reserved
Configuration
Reserved
User Data Memory
(Data EEPROM)
Reserved
Revision ID/
Device ID
00 0000h
•••
01 FFFFh
20 0000h
•••
20 000Fh
20 0010h
2F FFFFh
30 0000h
•••
30 000Bh
30 000Ch
30 FFFFh
31 0000h
•••
31 03FFh
32 0000h
3F FFFBh
3F FFFCh
•••
3F FFFFh
Read
10
No Access
x1
No Access
No Access
x1
No Access
No Access
00
No Access
No Access
x1
Read/
Write⁽¹⁾
Read/
Write
—⁽³⁾
Read/
Write
—⁽³⁾
—⁽³⁾
—⁽³⁾
Read
—⁽³⁾
—⁽³⁾
—⁽³⁾
Read/
Write
—⁽³⁾
Note 1: Subject to Memory Write Protection settings.
2: User IDs are eight words ONLY. There is no code protection, table read protection or write protection
implemented for this region.
3: Reads as ‘0’, writes clear the WR bit and WRERR bit is set.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 123