PIC18LF24K Datasheet, PDF (170/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 14-2: PIR0: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 0
U-0
U-0
R/W-0/0
R-0/0
U-0
R/W-0/0
R/W-0/0
—
—
TMR0IF⁽¹⁾ IOCIF^(1,2)
—
INT2IF^(1,3)
INT1IF^(1,3)
bit 7
R/W-0/0
INT0IF^(1,3)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR0IF: Timer0 Interrupt Flag bit⁽¹⁾
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register has not overflowed
IOCIF: Interrupt-on-Change Flag bit^(1,2)
1 = IOC event has occurred (must be cleared by software)
0 = IOC event has not occurred
Unimplemented: Read as ‘0’
INT2IF: External Interrupt 2 Flag bit^(1,3)
1 = External Interrupt 2 has occurred
0 = External Interrupt 2 has not occurred
INT1IF: External Interrupt 1 Flag bit^(1,3)
1 = External Interrupt 1 has occurred
0 = External Interrupt 1 has not occurred
INT0IF: External Interrupt 0 Flag bit^(1,3)
1 = External Interrupt 0 has occurred
0 = External Interrupt 0 has not occurred
Note 1: Interrupts are not disabled by the PEIE bit in the INTCON register.
2: IOCIF is a read-only bit, to clear the interrupt condition, all bits in the IOCF register must be cleared.
3: The external interrupt GPIO pin is selected by the INTPPS register.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 170