PIC18LF24K Datasheet, PDF (477/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 33-2: HLVDCON0: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER 0
R/W-0/0
U-0
R-x
R-x
U-0
U-0
R/W-0/0
EN
—
OUT
RDY
—
—
INTH
bit 7
R/W-0/0
INTL
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1
bit 0
EN: High/Low-voltage Detect Power Enable bit
1 = Enables HLVD, powers up HLVD circuit and supporting reference circuitry
0 = Disables HLVD, powers down HLVD and supporting circuitry
Unimplemented: Read as ‘0’
OUT: HLVD Comparator Output bit
1 = Voltage  selected detection limit (HLVDL<3:0>)
0 = Voltage  selected detection limit (HLVDL<3:0>)
RDY: Band Gap Reference Voltages Stable Status Flag bit
1 = Indicates HLVD Module is ready and output is stable
0 = Indicates HLVD Module is not ready
Unimplemented: Read as ‘0’
INTH: HLVD Positive going (High Voltage) Interrupt Enable
1 = HLVDIF will be set when voltage  selected detection limit (HLVDSEL<3:0>)
0 = HLVDIF will not be set
INTL: HLVD Negative going (Low Voltage) Interrupt Enable
1 = HLVDIF will be set when voltage  selected detection limit (HLVDSEL<3:0>)
0 = HLVDIF will not be set
TABLE 33-2: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
HLVDCON0
EN
—
OUT
RDY
—
—
INTH
INTL
477
HLVDCON1
—
—
—
—
INTCON
GIE/GIEH PEIE/GIEL IPEN
—
PIR2
HLVDIF ZCDIF
—
—
PIE2
HLVDIE ZCDIE
—
—
IPR2
HLVDIP ZCDIP
—
—
SEL<3:0>
476
—
INT2EDG INT1EDG INT0EDG
169
—
—
C2IF
C1IF
172
—
—
C2IE
C1IE
180
—
—
C2IP
C1IP
188
PMD0
SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD
67
Legend:
Note 1:
— = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 477