PIC18LF24K Datasheet, PDF(330/594 Page) –

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PIC18LF24K Datasheet, PDF (330/594 Pages) –

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PIC18(L)F26/45/46K40

FIGURE 26-1:

MSSP BLOCK DIAGRAM (SPI MODE)

Read

Data Bus

Write

SSPxDATPPS

SDI

PPS

SDO

PPS

RxyPPS

SS

PPS

SSPxSSPPS

SSPxBUF Reg

SSPSR Reg

bit 0

Shift

Clock

SS Control

Enable

Edge

Select

2 (CKP, CKE)

Clock Select

SSPxCLKPPS(2)

SCK

PPS

TRIS bit

PPS

RxyPPS(1)

Note 1: Output selection for master mode

2: Input selection for slave mode

Edge

Select

SSPM<3:0>

4

( ) T2_match

2

Prescaler TOSC

4, 16, 64

Baud Rate

Generator

(SSPxADD)

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select

connection is required from the master device to each

slave device.

Figure 26-2 shows a typical connection between a

master device and multiple slave devices.

The master selects only one slave at a time. Most slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

ï£ 2016 Microchip Technology Inc.

Preliminary

DS40001816C-page 330

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