PIC18LF24K Datasheet, PDF (412/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 27-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RXx/DTx
pin
TXx/CKx pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCxIF bit
(Interrupt)
Read
RCxREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 27-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELB
ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 203
ANSELC
ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 203
BAUDxCON ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
390
INTCON
GIE/GIEH PEIE/GIEL IPEN
—
—
INT2EDG INT1EDG INT0EDG 169
PIE3
RC2IE
TX2IE
RC1IE
TX1IE
BCL2IE SSP2IE BCL1IE SSP1IE
181
PIR3
RC2IF
TX2IF
RC1IF
TX1IF
BCL2IF SSP2IF BCL1IF SSP1IF
IPR3
RC2IP
TX2IP
RC1IP
TX1IP
BCL2IP SSP2IP BCL1IP SSP1IP
RCxREG
EUSARTx Receive Data Register
RCxSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RxyPPS
—
—
—
RxyPPS<4:0>
RXxPPS
—
—
—
RXPPS<4:0>
SPxBRGH
EUSARTx Baud Rate Generator, High Byte
SPxBRGL
EUSARTx Baud Rate Generator, Low Byte
TXxSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
173
189
394*
389
217
215
399*
399*
388
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 412