PIC18LF24K Datasheet, PDF (56/594 Pages) –

PIC18(L)F26/45/46K40
5.5 Register Definitions: Reference Clock
Long bit name prefixes for the Reference Clock periph-
erals are shown in Table 5-1. Refer to Section
1.4.2.2 “Long Bit Names” for more information.
TABLE 5-1:
Peripheral
Bit Name Prefix
CLKR
CLKR
REGISTER 5-1:
R/W-0/0
EN
bit 7
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
U-0
U-0
R/W-1/1
R/W-0/0
R/W-0/0
—
—
DC<1:0>
R/W-0/0
DIV<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-5
bit 4-3
bit 2-0
EN: Reference Clock Module Enable bit
1 = Reference clock module enabled
0 = Reference clock module is disabled
Unimplemented: Read as ‘0’
DC<1:0>: Reference Clock Duty Cycle bits⁽¹⁾
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
DIV<2:0>: Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value
Note 1: Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 56