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| PIC18LF24K Datasheet, PDF (178/594 Pages) – | |||
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PIC18(L)F26/45/46K40
REGISTER 14-10: PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0
U-0
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
â
â
TMR0IE(1) IOCIE(1)
â
INT2IE(1)
bit 7
R/W-0/0
INT1IE(1)
R/W-0/0
INT0IE(1)
bit 0
Legend: IE
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented bit, read as â0â
â0â = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as â0â
TMR0IE: Timer0 Interrupt Enable bit(1)
1 = Enabled
0 = Disabled
IOCIE: Interrupt-on-Change Enable bit(1)
1 = Enabled
0 = Disabled
Unimplemented: Read as â0â
INT2IE: External Interrupt 2 Enable bit(1)
1 = Enabled
0 = Disabled
INT1IE: External Interrupt 1 Enable bit(1)
1 = Enabled
0 = Disabled
INT0IE: External Interrupt 0 Enable bit(1)
1 = Enabled
0 = Disabled
Note 1: PIR0 interrupts are not disabled by the PEIE bit in the INTCON register. are not disabled by the PEIE bit
in the INTCON register.
ï£ 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 178
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