PIC18LF24K Datasheet, PDF (10/594 Pages) –

TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18(L)F45/46K40) (CONTINUED)
I/O⁽²⁾
RC2
17
32
36
36 ANC2
—
RC3
18
33
37
37 ANC3
—
RC4
23
38
42
42 ANC4
—
RC5
24
39
43
43 ANC5
—
RC6
25
40
44
44 ANC6
—
RC7
26
1
1
1
ANC7
—
—
T5CKI⁽¹⁾ CCP1⁽¹⁾
—
—
IOCC2
—
—
—
Y
—
—
T2AIN⁽¹⁾
—
—
—
IOCC3
—
—
SCK1⁽¹⁾
Y
—
SCL1^(3,4)
—
—
—
—
—
IOCC4
—
—
SDI1⁽¹⁾
—
—
SDA1^(3,4)
—
T4AIN⁽¹⁾
—
—
—
IOCC5
—
—
—
Y
—
—
—
—
—
—
IOCC6
CK1⁽¹⁾
—
—
Y
—
—
—
—
—
—
IOCC7 RX1/DT1⁽¹⁾
—
—
Y
—
RD0
19
34
38
38 AND0
—
—
—
—
—
—
IOCD0
—
—
—
Y
—
RD1
20
35
39
39 AND1
—
—
—
—
—
—
IOCD1
—
—
—
Y
—
RD2
21
36
40
40 AND2
—
—
—
—
—
—
IOCD2
—
—
—
Y
—
RD3
22
37
41
41 AND3
—
—
—
—
—
—
IOCD3
—
—
—
Y
—
RD4
27
2
2
2
AND4
—
—
—
—
—
—
IOCD4
—
—
—
Y
—
RD5
28
3
3
3
AND5
—
—
—
—
—
—
IOCD5
—
—
—
Y
—
RD6
29
4
4
4
AND6
—
—
—
—
—
—
IOCD6
—
—
—
Y
—
RD7
30
5
5
5
AND7
—
—
—
—
—
—
IOCD7
—
—
—
Y
—
RE0
8
23
25
25 ANE0
—
—
—
—
—
—
—
—
—
—
Y
—
RE1
9
24
26
26 ANE1
—
—
—
—
—
—
—
—
—
—
Y
—
RE2
10
25
27
27 ANE2
—
—
—
—
—
—
—
—
—
—
Y
—
RE3
1
16
18
18
—
—
—
—
—
—
—
IOCE3
—
—
—
Y
VPP/MCLR
VSS
12
6
6
6
—
—
—
—
—
—
—
—
—
—
—
—
VSS
VDD
11
7
7
7
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VDD
32
26
28
28
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
31
27
30
29
—
—
—
—
—
—
—
—
—
—
OUT⁽²⁾ —
— ADGRDA — C1OUT
TMR0
CCP1 CWG1A
—
—
TX1/
DSM
SDO1
—
ADGRDB
C2OUT
CCP2 CWG1B
CK1⁽³⁾
SCK1
PWM3 CWG1C
DT1⁽³⁾
SDO2
PWM4 CWG1D
TX2/
CK2⁽³⁾
DT2⁽³⁾
SCK2
—
—
VSS
—
OUT⁽²⁾
—
Note 1:
2:
3:
4:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1).
All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be
standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.