PIC18LF24K Datasheet, PDF (131/594 Pages) –

PIC18(L)F26/45/46K40
11.1.5
ERASING PROGRAM FLASH
MEMORY
The minimum erase block is 32 or 64 words (refer to
Table 11-3). Only through the use of an external
programmer, or through ICSP™ control, can larger
blocks of program memory be bulk erased. Word erase
in the Flash array is not supported.
For example, when initiating an erase sequence from a
microcontroller with erase row size of 32 words, a block
of 32 words (64 bytes) of program memory is erased.
The Most Significant 16 bits of the TBLPTR<21:6>
point to the block being erased. The TBLPTR<5:0> bits
are ignored.
The NVMCON1 register commands the erase
operation. The NVMREG<1:0> bits must be set to point
to the Program Flash Memory. The WREN bit must be
set to enable write operations. The FREE bit is set to
select an erase operation.
The NVM unlock sequence described in Section
11.1.4 “NVM Unlock Sequence” should be used to
guard against accidental writes. This is sometimes
referred to as a long write.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted during the long write
cycle. The long write is terminated by the internal
programming timer.
11.1.5.1
Program Flash Memory Erase
Sequence
The sequence of events for erasing a block of internal
program memory is:
1. NVMREG bits of the NVMCON1 register point to
PFM
2. Set the FREE and WREN bits of the NVMCON1
register
3. Perform the unlock sequence as described in
Section 11.1.4 “NVM Unlock Sequence”
If the PFM address is write-protected, the WR bit will be
cleared and the erase operation will not take place,
WRERR is signaled in this scenario.
The operation erases the memory row indicated by
masking the LSBs of the current TBLPTR.
While erasing PFM, CPU operation is suspended and
it resumes when the operation is complete. Upon
completion the WR bit is cleared in hardware, the
NVMIF is set and an interrupt will occur if the NVMIE bit
is also set.
Write latch data is not affected by erase operations and
WREN will remain unchanged.
Note 1: If a write or erase operation is terminated
by an unexpected event, WRERR bit will
be set which the user can check to decide
whether a rewrite of the location(s) is
needed.
2: WRERR is set if WR is written to ‘1’ while
TBLPTR points to a write-protected
address.
3: WRERR is set if WR is written to ‘1’ while
TBLPTR points to an invalid address
location (Table 10-1 and Table 11-1).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 131