PIC18LF24K Datasheet, PDF (126/594 Pages) –

PIC18(L)F26/45/46K40
11.1.2 CONTROL REGISTERS
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the
following registers:
• NVMCON1 register
• NVMCON2 register
• TABLAT register
• TBLPTR registers
11.1.2.1 NVMCON1 and NVMCON2
Registers
The NVMCON1 register (Register 11-1) is the control
register for memory accesses. The NVMCON2 register
is not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
NVMCON2 will read all ‘0’s.
The NVMREG<1:0> control bits determine if the
access will be to Data EEPROM Memory locations.
PFM locations or User IDs, Configuration bits, Rev ID
and Device ID. When NVMREG<1:0> = 00, any
subsequent operations will operate on the Data
EEPROM Memory. When NVMREG<1:0> = 10, any
subsequent operations will operate on the program
memory. When NVMREG<1:0> = x1, any subsequent
operations will operate on the Configuration bits, User
IDs, Rev ID and Device ID.
The FREE bit allows the program memory erase
operation. When the FREE bit is set, an erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled. This bit is
applicable only to the PFM and not to data EEPROM.
When set, the WREN bit will allow a program/erase
operation. The WREN bit is cleared on power-up.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is successfully
complete.
The WR control bit initiates erase/write cycle operation
when the NVMREG<1:0> bits point to the Data
EEPROM Memory location, and it initiates a write
operation when the NVMREG<1:0> bits point to the
PFM location. The WR bit cannot be cleared by
firmware; it can only be set by firmware. Then the WR
bit is cleared by hardware at the completion of the write
operation.
The NVMIF Interrupt Flag bit of the PIR7 register is set
when the write is complete. The NVMIF flag stays set
until cleared by firmware.
11.1.2.2 TABLAT – Table Latch Register
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
11.1.2.3 TBLPTR – Table Pointer Register
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three
registers join to form a 22-bit wide pointer. The low-
order 21 bits allow the device to address up to 2 Mbytes
of program memory space. The 22^nd bit allows access
to the Device ID, the User ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations on the TBLPTR
affect only the low-order 21 bits.
11.1.2.4 Table Pointer Boundaries
TBLPTR is used in reads, writes and erases of the
Program Flash Memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT is executed the byte in the TABLAT
register is written, not to Flash memory but, to a holding
register in preparation for a program memory write. The
holding registers constitute a write block which varies
depending on the device (see Table 11-3).The 3, 4, or
5 LSbs of the TBLPTRL register determine which
specific address within the holding register block is
written to. The MSBs of the Table Pointer have no effect
during TBLWT operations.
When a program memory write is executed the entire
holding register block is written to the Flash memory at
the address determined by the MSbs of the TBLPTR.
The 3, 4, or 5 LSBs are ignored during Flash memory
writes. For more detail, see Section 11.1.6 “Writing to
Program Flash Memory”.
Figure 11-3 describes the relevant boundaries of
TBLPTR based on Program Flash Memory operations.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 126