PIC18LF24K Datasheet, PDF (292/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 24-1:
SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE, MODE<2:0> = 100)
LSAC<1:0>
Rev. 10-000209C
8/7/2015
CWG Clock
CWG Data
Rising Dead-Band Block
clock
data out
data in
CWG Data A
‘1’ 00
‘0’ 01
High-Z 10
11
POLA
1
0 CWG1A
LSBD<1:0>
Falling Dead-Band Block
clock
data out
data in
CWG Data B
CWG Data Input
DQ
E
CWG
Data
‘1’ 00
‘0’ 01
High-Z ¹⁰
11
POLB
LSAC<1:0>
1
0 CWG1B
EN
SHUTDOWN = 1
AS0E
PPS
CWG1PPS
AS1E
TMR2_postscaled
AS2E
TMR4_postscaled
AS3E
TMR6_postscaled
AS4E
CMP1OUT
AS5E
CMP2OUT
REN
SHUTDOWN = 0
‘1’ 00
‘0’ 01
High-Z 10
11
Auto-
shutdown
source
POLC
LSBD<1:0>
SQ
R
SHUTDOWN
FREEZE
‘1’ 00
‘0’ 01
High-Z 10
11
POLD
CWG Data
DQ
1
0 CWG1C
1
0 CWG1D
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 292