PIC18LF24K Datasheet, PDF (301/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 24-11: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)
MODE<2:0> = 000: Asynchronous
MODE<2:0> = 001: Synchronous
LSAC<1:0>
CWG Data A
POLA
‘1’ 00
‘0’ 01
High-Z 10
11
DATA
STRA
1
0
LSBD<1:0>
Rev. 10-000211C
8/7/2015
1
0 CWG1A
CWG Data
Input
EN
DQ
E
CWG
Data
CWG Data B
POLB
‘1’ 00
‘0’ 01
High-Z ¹⁰
11
DATB
STRB
1
0
LSAC<1:0>
1
0 CWG1B
SHUTDOWN = 1
AS0E
PPS
CWG1PPS
AS1E
TMR2_postscaled
AS2E
TMR4_postscaled
AS3E
TMR6_postscaled
AS4E
CMP1OUT
AS5E
CMP2OUT
REN
SHUTDOWN = 0
Auto-
shutdown
source
CWG Data C
POLC
‘1’ 00
‘0’ 01
High-Z 10
11
DATC
STRC
1
0
LSBD<1:0>
SQ
R
SHUTDOWN
FREEZE
CWG Data D
POLD
DATD
CWG Data
DQ
‘1’ 00
‘0’ 01
High-Z 10
11
1
0
STRD
1
0 CWG1C
1
0 CWG1D
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 301