PIC18LF24K Datasheet, PDF (16/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 1-1:
PIC18(L)F2X/4XK40 FAMILY BLOCK DIAGRAM
Table Pointer<21>
inc/dec logic
Data Bus<8>
88
21
PCLATU PCLATH
20
PCU PCH PCL
Program Counter
Address Latch
Program Memory
(8/16/32/64 Kbytes)
Data Latch
31-Level Stack
STKPTR
8
Table Latch
ROM Latch
Instruction Bus <16>
IR
Data Latch
Data Memory
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Access
Bank
12
inc/dec
logic
Address
Decode
OSC1⁽²⁾
OSC2⁽²⁾
SOSCI
SOSCO
MCLR⁽¹⁾
Instruction
Decode and
Control
State machine
control signals
Internal
Oscillator
Block
LFINTOSC
Oscillator
64 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
8
PRODH PRODL
3
BITOP
8
8x8 Multiply
8
W
8
8
8
8
ALU<8>
8
Precision
Band Gap
Reference
FVR
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer3
Timer5
Timer2
Timer4
Timer6
ZCD CRC-Scan
PORTA
RA<7:0>
PORTB
RB<7:0>
PORTC
RC<7:0>
PORTD
RD<7:0>
PORTE
RE<2:0>
RE3⁽¹⁾
DAC
FVR _{Comparators CCP1}
DAC
C1/C2
CCP2
PWM3
PWM4
MSSP1 EUSART1
MSSP2 EUSART2
ECWG
DSM
PMD
ADC
10-bit
FVR
Note 1: RE3 is only available when MCLR functionality is disabled.
2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 4.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional information.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 16