PIC18LF24K Datasheet, PDF (467/594 Pages) –

PIC18(L)F26/45/46K40
32.4 Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
See Comparator Specifications in Table 37-15 for more
information.
32.5 Timer1/3/5 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1/3/5. See
Section 19.8 “Timer1/3/5 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
32.5.1
COMPARATOR OUTPUT
SYNCHRONIZATION
The output from a comparator can be synchronized
with Timer1 by setting the SYNC bit of the CMxCON0
register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 32-2) and the Timer1 Block
Diagram (Figure 19-1) for more information.
32.6 Comparator Interrupt
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• EN and POL bits of the CMxCON0 register
• CxIE bit of the PIE2 register
• INTP bit of the CMxCON1 register (for a rising
edge detection)
• INTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxEN bit
of the CMxCON0 register.
32.7 Comparator Positive Input
Selection
Configuring the PCH<2:0> bits of the CMxPCH register
directs an internal voltage reference or an analog pin to
the non-inverting input of the comparator:
• CxIN0+, CxIN1+ analog pin
• DAC output
• FVR (Fixed Voltage Reference)
• AVSS (Ground)
See Section 28.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 30.0 “5-Bit Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxEN = 0), all
comparator inputs are disabled.
32.8 Comparator Negative Input
Selection
The NCH<2:0> bits of the CMxNCH register direct an
analog input pin and internal reference voltage or ana-
log ground to the inverting input of the comparator:
• CxIN0-, CxIN1-, CxIN2-, CxIN3- analog pin
• FVR (Fixed Voltage Reference)
• Analog Ground
Note:
To use CxINy+ and CxINy- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the correspond-
ing TRIS bits must also be set to disable
the output drivers.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 467