PIC18LF24K Datasheet, PDF (321/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 25-2: MDCON1: MODULATION CONTROL REGISTER 1
U-0
U-0
R/W-0/0
R/W-0/0
U-0
U-0
—
—
CHPOL
CHSYNC
—
—
bit 7
R/W-0/0
CLPOL
R/W-0/0
CLSYNC
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
bit 4
bit 3-2
bit 1
bit 0
Unimplemented: Read as ‘0’
CHPOL: Modulator High Carrier Polarity Select bit
1 = Selected high carrier signal is inverted
0 = Selected high carrier signal is not inverted
CHSYNC: Modulator High Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the
low time carrier
0 = Modulator output is not synchronized to the high time carrier signal⁽¹⁾
Unimplemented: Read as ‘0’
CLPOL: Modulator Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
CLSYNC: Modulator Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
time carrier
0 = Modulator output is not synchronized to the low time carrier signal⁽¹⁾
Note 1:Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 321