PIC18LF24K Datasheet, PDF (132/594 Pages) –

PIC18(L)F26/45/46K40
EXAMPLE 11-3: ERASING A PROGRAM FLASH MEMORY BLOCK
; This sample row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in variables TBLPTR register
; 2. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
ERASE_BLOCK
BCF
BSF
BSF
BSF
BCF
Required MOVLW
Sequence MOVWF
MOVLW
MOVWF
BSF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
NVMCON1, NVMREG0
NVMCON1, NVMREG1
NVMCON1, WREN
NVMCON1, FREE
INTCON, GIE
55h
NVMCON2
AAh
NVMCON2
NVMCON1, WR
INTCON, GIE
; point to Program Flash Memory
; access Program Flash Memory
; enable write to memory
; enable block Erase operation
; disable interrupts
; write 55h
; write AAh
; start erase (CPU stalls)
; re-enable interrupts
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 132