PIC18LF24K Datasheet, PDF (140/594 Pages) –

PIC18(L)F26/45/46K40
11.3 Data EEPROM Memory
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory,
which is used for long-term storage of program data. It
is not directly mapped in either the register file or
program memory space but is indirectly addressed
through the Special Function Registers (SFRs). The
EEPROM is readable and writable during normal
operation over the entire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• NVMCON1
• NVMCON2
• NVMDAT
• NVMADRL
• NVMADRH(1)
Note 1: NVMADRH register is not implemented
on PIC18(L)F45K40.
The data EEPROM allows byte read and write. When
interfacing to the data memory block, NVMDAT holds
the 8-bit data for read/write and the
NVMADRH:NVMADRL register pair hold the address
of the EEPROM location being accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an internal programming
timer; it will vary with voltage and temperature as well as
from chip-to-chip. Please refer to the Data EEPROM
Memory parameters in Section 37.0 “Electrical
Specifications” for limits.
11.3.1
NVMADRL AND NVMADRH
REGISTERS
The NVMADRH:NVMADRL registers are used to
address the data EEPROM for read and write
operations.
11.3.2
NVMCON1 AND NVMCON2
REGISTERS
Access to the data EEPROM is controlled by two
registers: NVMCON1 and NVMCON2. These are the
same registers which control access to the program
memory and are used in a similar manner for the data
EEPROM.
The NVMCON1 register (Register 11-1) is the control
register for data and program memory access. Control
bits NVMREG<1:0> determine if the access will be to
program, Data EEPROM Memory or the User IDs,
Configuration bits, Revision ID and Device ID.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
The WR control bit initiates write operations. The bit
can be set but not cleared by software. It is cleared only
by hardware at the completion of the write operation.
The NVMIF interrupt flag bit of the PIR7 register is set
when the write is complete. It must be cleared by
software.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (NVMREG<1:0> = 0x10). Program memory is
read using table read instructions. See Section
11.1.1 “Table Reads and Table Writes” regarding
table reads.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 140