PIC18LF24K Datasheet, PDF (191/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 14-23: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
U-0
U-0
U-0
U-0
U-0
R/W-1/1
R/W-1/1
—
—
—
—
—
TMR5GIP TMR3GIP
bit 7
R/W-1/1
TMR1GIP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR5GIP: TMR5 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
TMR3GIP: TMR3 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
TMR1GIP: TMR1 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 191