PIC18LF24K Datasheet, PDF (351/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 26-9: SSPxCON3: MSSPx CONTROL REGISTER 3 (I²C MASTER MODE)
R/HS/HC-0
ACKTIM
bit 7
R/W-0
PCIE
R/W-0
SCIE
R/W-0
BOEN
R/W-0
SDAHT
R/W-0
SBCDE
R/W-0
AHEN
R/W-0
DHEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
x = Bit is unknown
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
HS/HC = Bit is set/cleared by hardware
bit 7
ACKTIM: Acknowledge Time Status bit
Unused in Master mode.
bit 6
PCIE: Stop Condition Interrupt Enable bit⁽¹⁾
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 5
SCIE: Start Condition Interrupt Enable bit⁽¹⁾
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 4
BOEN: Buffer Overwrite Enable bit
1 = SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV effect on
updating the buffer
0 = SSPxBUF is only updated when SSPOV is clear
bit 3
SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100ns hold time on SDA after the falling edge of SCL
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit
Unused in Master mode.
bit 1
AHEN: Address Hold Enable bit
Unused in Master mode.
bit 0
DHEN: Data Hold Enable bit
Unused in Master mode.
Note 1: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
REGISTER 26-10: SSPxBUF: MSSP DATA BUFFER REGISTER (I²C MASTER MODE)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
BUF<7:0>
bit 7
R/W-x
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
BUF<7:0>: MSSP Buffer bits
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 351