PIC18LF24K Datasheet, PDF (85/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 9-2: WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1
U-0
R/W⁽³⁾-q/q⁽¹⁾ R/W⁽³⁾-q/q⁽¹⁾ R/W⁽³⁾-q/q⁽¹⁾
U-0
R/W⁽⁴⁾-q/q⁽²⁾ R/W⁽⁴⁾-q/q⁽²⁾
—
WDTCS<2:0>
—
WINDOW<2:0>
bit 7
R/W⁽⁴⁾-q/q⁽²⁾
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6-4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
WDTCS<2:0>: Watchdog Timer Clock Select bits
111 = Reserved
•
•
•
010 = Reserved
001 = MFINTOSC 31.25 kHz
000 = LFINTOSC 31 kHz
Unimplemented: Read as ‘0’
WINDOW<2:0>: Watchdog Timer Window Select bits
WINDOW_<2:0>
111
110
101
100
011
010
001
000
Window delay
Percent of time
N/A
12.5
25
37.5
50
62.5
75
87.5
Window opening
Percent of time
100
87.5
75
62.5
50
37.5
25
12.5
Note 1:
2:
3:
4:
If WDTCCS <2:0> in CONFIG3H = 111, the Reset value of WDTCS<2:0> is 000.
The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3H
register.
If WDTCCS<2:0> in CONFIG3H ≠ 111, these bits are read-only.
If WDTCWS<2:0> in CONFIG3H ≠ 111, these bits are read-only.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 85