PIC18LF24K Datasheet, PDF (347/594 Pages) –

PIC18(L)F26/45/46K40
26.6.2 ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a trans-
mission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses arbitra-
tion, and must stop transmitting on the SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
26.7 Register Definitions: I²C Mode
The MSSPx module has seven registers for I²C
operation.
These are:
• MSSP Status Register (SSPxSTAT)
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Control Register 3 (SSPxCON3)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSP Address Register (SSPxADD)
• I²C Slave Address Mask Register (SSPxMSK)
• MSSP Shift Register (SSPSR) – not directly
accessible
SSPxCON1, SSPxCON2, SSPxCON3 and SSPxSTAT
are the Control and Status registers in I²C mode
operation. The SSPxCON1, SSPxCON2, and
SSPxCON3 registers are readable and writable. The
lower six bits of the SSPxSTAT are read-only. The
upper two bits of the SSPxSTAT are read/write.
SSPSR is the Shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from. SSPxADD contains
the slave device address when the MSSP is
configured in I²C Slave mode. When the MSSP is
configured in Master mode, the lower seven bits of
SSPxADD act as the Baud Rate Generator reload
value.
SSPxMSK holds the slave address mask value when
the module is configured for 7-Bit Address Masking
mode. While it is a separate register, it shares the
same SFR address as SSPxADD; it is only accessible
when the SSPM<3:0> bits are specifically set to permit
access. In receive operations, SSPSR and SSPxBUF
together, create a double-buffered receiver. When
SSPSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set. During
transmission, the SSPxBUF is not double-buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPSR.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 347