PIC18LF24K Datasheet, PDF (293/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 24-2:
CWG1 HALF-BRIDGE MODE OPERATION
CWGx_clock
CWGxA
CWGxC
CWGxB
CWGxD
Rising Event Dead Band
Rising Event D
Falling Event Dead Band
Falling Event Dead Band
CWGx_data
Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out
24.2.2 PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 24-4. This alternation creates the push-pull
effect required for driving some transformer-based
power supply designs. Steering modes are not used in
Push-Pull mode. A basic block diagram for the
Push-Pull mode is shown in Figure 24-3.
The push-pull sequencer is reset whenever EN = 0 or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWG1A.
The unused outputs CWG1C and CWG1D drive copies
of CWG1A and CWG1B, respectively, but with polarity
controlled by the POLC and POLD bits of the
CWG1CON1 register, respectively.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 293