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| PIC18LF24K Datasheet, PDF (313/594 Pages) – | |||
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PIC18(L)F26/45/46K40
REGISTER 24-5: CWG1STR(1): CWG STEERING CONTROL REGISTER
R/W-0/0
OVRD
R/W-0/0
OVRC
R/W-0/0
OVRB
R/W-0/0
OVRA
R/W-0/0
STRD(2)
R/W-0/0
STRC(2)
bit 7
R/W-0/0
STRB(2)
R/W-0/0
STRA(2)
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
â1â = Bit is set
W = Writable bit
x = Bit is unknown
â0â = Bit is cleared
U = Unimplemented bit, read as â0â
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
OVRD: Steering Data D bit
bit 6
OVRC: Steering Data C bit
bit 5
OVRB: Steering Data B bit
bit 4
OVRA: Steering Data A bit
bit 3
STRD: Steering Enable bit D(2)
1 = CWG1D output has the CWG data input waveform with polarity control from POLD bit
0 = CWG1D output is assigned to value of OVRD bit
bit 2
STRC: Steering Enable bit C(2)
1 = CWG1C output has the CWG data input waveform with polarity control from POLC bit
0 = CWG1C output is assigned to value of OVRC bit
bit 1
STRB: Steering Enable bit B(2)
1 = CWG1B output has the CWG data input waveform with polarity control from POLB bit
0 = CWG1B output is assigned to value of OVRB bit
bit 0
STRA: Steering Enable bit A(2)
1 = CWG1A output has the CWG data input waveform with polarity control from POLA bit
0 = CWG1A output is assigned to value of OVRA bit
Note 1: The bits in this register apply only when MODE<2:0> = 00x (Register 24-1, Steering modes).
2: This bit is double-buffered when MODE<2:0> = 001.
ï£ 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 313
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