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PIC18LF24K Datasheet, PDF (488/594 Pages) – | |||
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PIC18(L)F26/45/46K40
ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
AND W with f
ANDWF f {,d {,a}}
0 ï£ f ï£ 255
d ïï [0,1]
a ïï [0,1]
(W) .AND. (f) ï® dest
N, Z
0001 01da ffff ffff
The contents of W are ANDâed with
register âfâ. If âdâ is â0â, the result is stored
in W. If âdâ is â1â, the result is stored back
in register âfâ (default).
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See Sec-
tion 35.2.3 âByte-Oriented and Bit-
Oriented Instructions in Indexed Lit-
eral Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example:
ANDWF
Before Instruction
W
= 17h
REG = C2h
After Instruction
W
REG
= 02h
= C2h
REG, 0, 0
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
Branch if Carry
BC n
-128 ï£ n ï£ 127
if CARRY bit is â1â
(PC) + 2 + 2n ï® PC
None
1110 0010 nnnn nnnn
If the CARRY bit is â1â, then the program
will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
2-cycle instruction.
1
1(2)
Q2
Read literal
ânâ
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
ânâ
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If CARRY =
PC
=
If CARRY =
PC
=
BC 5
address (HERE)
1;
address (HERE + 12)
0;
address (HERE + 2)
ï£ 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 488
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