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| PIC18LF24K Datasheet, PDF (243/594 Pages) – | |||
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PIC18(L)F26/45/46K40
FIGURE 20-2:
TxRSEL <3:0>
TxINPPS
TxIN PPS
TIMER2 WITH HARDWARE LIMIT TIMER (HLT) BLOCK DIAGRAM
TxMODE<4:0>
MODE<3>
External
Reset
Sources(2)
TMRx_ers
Edge Detector
Level Detector
Mode Control
(2 clock Sync)
reset
Rev. 10-000168C
9/10/2015
CCP_pset(1)
TxCPOL
TMRx_clk
TxON
Sync
(2 Clocks)
1
0
enable
MODE<4:3>=01
MODE<4:1>=1011
Clear ON
DQ
Prescaler
0
3
Sync
1
TxCKPS<2:0> Fosc/4 TxPSYNC
TMRx R
Set flag bit
TMRxIF
Comparator
TMRx_postscaled
Postscaler
4
PRx
TxOUTPS<3:0>
TxCSYNC
Note 1: Signal to the CCP to trigger the PWM pulse.
2: See TxRST Register 20-6 for external Reset sources.
ï£ 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 243
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