PIC18LF24K Datasheet, PDF (88/594 Pages) –

PIC18(L)F26/45/46K40
9.2 Independent Clock Source
The WWDT can derive its time base from either the
31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal
oscillators, depending on the value of WDTE<1:0>
Configuration bits.
If WDTE = 2'b1x, then the clock source will be
enabled depending on the WDTCCS<2:0>
Configuration bits.
If WDTE = 2'b01, the SEN bit should be set by
software to enable WWDT, and the clock source is
enabled by the WDTCS bits in the WDTCON1 register.
Time intervals in this chapter are based on a minimum
nominal interval of 1 ms. See Section 37.0 “Electrical
Specifications” for LFINTOSC and MFINTOSC
tolerances.
9.3 WWDT Operating Modes
The Windowed Watchdog Timer module has four
operating modes controlled by the WDTE<1:0> bits in
Configuration Words. See Table 9-1.
9.3.1 WWDT IS ALWAYS ON
When the WDTE bits of Configuration Words are set to
‘11’, the WWDT is always on.
WWDT protection is active during Sleep.
9.3.2 WWDT IS OFF IN SLEEP
When the WDTE bits of Configuration Words are set to
‘10’, the WWDT is on, except in Sleep.
WWDT protection is not active during Sleep.
9.3.3
WWDT CONTROLLED BY
SOFTWARE
When the WDTE bits of Configuration Words are set to
‘01’, the WWDT is controlled by the SEN bit of the
WDTCON0 register.
WWDT protection is unchanged by Sleep. See
Table 9-1 for more details.
TABLE 9-1:
WDTE<1:0>
11
10
01
00
WWDT OPERATING MODES
SEN
Device
Mode
WWDT
Mode
X
X
Active
Awake Active
X
Sleep Disabled
1
X
Active
0
X
Disabled
X
X
Disabled
9.4 Time-out Period
If the WDTCPS<4:0> Configuration bits default to
5'b11111, then the WDTPS bits of the WDTCON0
register set the time-out period from 1 ms to
256 seconds (nominal). If any value other than the
default value is assigned to WDTCPS<4:0>
Configuration bits, then the timer period will be based
on the WDTCPS<4:0> bits in the CONFIG3L register.
After a Reset, the default time-out period is 2s.
9.5 Watchdog Window
The Windowed Watchdog Timer has an optional
Windowed mode that is controlled by the
WDTCWS<2:0> Configuration bits and WINDOW<2:0>
bits of the WDTCON1 register. In the Windowed mode,
the CLRWDT instruction must occur within the allowed
window of the WDT period. Any CLRWDT instruction that
occurs outside of this window will trigger a window
violation and will cause a WWDT Reset, similar to a
WWDT time out. See Figure 9-2 for an example.
The window size is controlled by the WINDOW<2:0>
Configuration bits, or the WINDOW<2:0> bits of
WDTCON1, if WDTCWS<2:0> = 111.
The five Most Significant bits of the WDTTMR register
are used to determine whether the window is open, as
defined by the WINDOW<2:0> bits of the WDTCON1
register.
In the event of a window violation, a Reset will be
generated and the WDTWV bit of the PCON0 register
will be cleared. This bit is set by a POR or can be set in
firmware.
9.6 Clearing the WWDT
The WWDT is cleared when any of the following
conditions occur:
• Any Reset
• Valid CLRWDT instruction is executed
• Device enters Sleep
• Exit Sleep by Interrupt
• WWDT is disabled
• Oscillator Start-up Timer (OST) is running
• Any write to the WDTCON0 or WDTCON1
registers
9.6.1
CLRWDT CONSIDERATIONS
(WINDOWED MODE)
When in Windowed mode, the WWDT must be armed
before a CLRWDT instruction will clear the timer. This is
performed by reading the WDTCON0 register.
Executing a CLRWDT instruction without performing
such an arming action will trigger a window violation
regardless of whether the window is open or not.
See Table 9-2 for more information.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 88