PIC18LF24K Datasheet, PDF (183/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 14-15: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
TMR5GIE
bit 7
R/W-0/0
TMR3GIE
R/W-0/0
TMR1GIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR5GIE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR3GIE: TMR3 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR1GIE: TMR1 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 183