PIC18LF24K Datasheet, PDF (235/594 Pages) –

PIC18(L)F26/45/46K40
19.7 Timer1/3/5 16-Bit Read/Write Mode
Timer1/3/5 can be configured to read and write all 16
bits of data, to and from, the 8-bit TMRxL and TMRxH
registers, simultaneously. The 16-bit read and write
operations are enabled by setting the RD16 bit of the
TxCON register.
To accomplish this function, the TMRxH register value
is mapped to a buffer register called the TMRxH buffer
register. While in 16-Bit mode, the TMRxH register is
not directly readable or writable and all read and write
operations take place through the use of this TMRxH
buffer register.
When a read from the TMRxL register is requested, the
value of the TMRxH register is simultaneously loaded
into the TMRxH buffer register. When a read from the
TMRxH register is requested, the value is provided
from the TMRxH buffer register instead. This provides
the user with the ability to accurately read all 16 bits of
the Timer1/3/5 value from a single instance in time.
Reference the block diagram in Figure 19-2 for more
details.
In contrast, when not in 16-Bit mode, the user must
read each register separately and determine if the
values have become invalid due to a rollover that may
have occurred between the read operations.
When a write request of the TMRxL register is
requested, the TMRxH buffer register is simultaneously
updated with the contents of the TMRxH register. The
value of TMRxH must be preloaded into the TMRxH
buffer register prior to the write request for the TMRxL
register. This provides the user with the ability to write
all 16 bits to the TMRxL:TMRxH register pair at the
same time.
Any requests to write to the TMRxH directly does not
clear the Timer1/3/5 prescaler value. The prescaler
value is only cleared through write requests to the
TMRxL register.
FIGURE 19-2:
TMR1L
TIMER1/3/5 16-BIT
READ/WRITE MODE
BLOCK DIAGRAM
TMR1
High Byte
8
From
Timer1
Circuitry
Set
TMR1IF
on Overflow
Read TMR1L
8
8
Write TMR1L
TMR1H
8
8
Internal Data Bus
Block Diagram of Timer1 Example of TIMER1/3/5
19.8 Timer1/3/5 Gate
Timer1/3/5 can be configured to count freely or the
count can be enabled and disabled using Timer1/3/5
gate circuitry. This is also referred to as Timer1/3/5 gate
enable.
Timer1/3/5 gate can also be driven by multiple
selectable sources.
19.8.1 TIMER1/3/5 GATE ENABLE
The Timer1/3/5 Gate Enable mode is enabled by
setting the TMRxGE bit of the TxGCON register. The
polarity of the Timer1/3/5 Gate Enable mode is
configured using the TxGPOL bit of the TxGCON
register.
When Timer1/3/5 Gate Enable mode is enabled,
Timer1/3/5 will increment on the rising edge of the
Timer1/3/5 clock source. When Timer1/3/5 Gate signal
is inactive, the timer will not increment and hold the
current count. Enable mode is disabled, no
incrementing will occur and Timer1/3/5 will hold the
current count. See Figure 19-4 for timing details.
TABLE 19-3: TIMER1/3/5 GATE ENABLE
SELECTIONS
TMRxCLK TxGPOL TxG
Timer1/3/5
Operation

1
1 Counts

1
0 Holds Count

0
1 Holds Count

0
0 Counts
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 235