PIC18LF24K Datasheet, PDF (369/594 Pages) –

PIC18(L)F26/45/46K40
26.9.6 CLOCK STRETCHING
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing communi-
cation. The slave may stretch the clock to allow more
time to handle data or prepare a response for the
master device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
26.9.6.1 Normal Clock Stretching
Following an ACK if the R/W bit of SSPxSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPxBUF was read before the ninth
falling edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPxBUF was loaded before the ninth
falling edge of SCL. It is now always
cleared for read requests.
26.9.6.2 10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set, the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPxADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
26.9.6.3 Byte NACKing
When the AHEN bit of SSPxCON3 is set; CKP is
cleared by hardware after the eighth falling edge of
SCL for a received matching address byte. When the
DHEN bit of SSPxCON3 is set; CKP is cleared after
the eighth falling edge of SCL for received data.
Stretching after the eighth falling edge of SCL allows
the slave to look at the received address or data and
decide if it wants to ACK the received data.
26.9.7
CLOCK SYNCHRONIZATION AND
THE CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
external I²C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I²C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 26-23).
FIGURE 26-23: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
CKP
WR
SSPxCON1
DX
Master device
asserts clock
Master device
releases clock
DX ‚ – 1
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 369