PIC18LF24K Datasheet, PDF (295/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 24-4:
CWG1 PUSH-PULL MODE OPERATION
CWG1
clock
Input
source
CWG1A
CWG1B
24.2.3 FULL-BRIDGE MODES
In Forward and Reverse Full-Bridge modes, three
outputs drive static values while the fourth is modulated
by the input data signal. The mode selection may be
toggled between forward and reverse by toggling the
MODE<0> bit of the CWG1CON0 while keeping
MODE<2:1> static, without disabling the CWG module.
When connected as shown in Figure 24-5, the outputs
are appropriate for a full-bridge motor driver. Each
CWG output signal has independent polarity control, so
the circuit can be adapted to high-active and low-active
drivers. A simplified block diagram for the Full-Bridge
modes is shown in Figure 24-6.
FIGURE 24-5:
EXAMPLE OF FULL-BRIDGE APPLICATION
VDD
Rev. 10-000263A
12/8/2015
CWG1A
CWG1B
CWG1C
CWG1D
FET
QA
Driver
FET
Driver
QB
LOAD
FET
QC
Driver
FET
Driver
QD
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 295