PIC18LF24K Datasheet, PDF (447/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 31-5: ADSTAT: ADC STATUS REGISTER
R-0/0
R-0/0
R-0/0 R/HS/HC-0/0
U-0
ADAOV
ADUTHR
ADLTHR
ADMATH
—
bit 7
R-0/0
R-0/0
ADSTAT<2:0>
R-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS/HC = Bit is set/cleared by hardware
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
ADAOV: ADC Accumulator Overflow bit
1 = ADC accumulator or ADERR calculation have overflowed
0 = ADC accumulator and ADERR calculation have not overflowed
ADUTHR: ADC Module Greater-than Upper Threshold Flag bit
1 = ADERR >ADUTH
0 = ADERRADUTH
ADLTHR: ADC Module Less-than Lower Threshold Flag bit
1 = ADERR<ADLTH
0 = ADERR≥ADLTH
ADMATH: ADC Module Computation Status bit
1 = Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have already
updated
0 = Associated registers/bits have not changed since this bit was last cleared
Unimplemented: Read as ‘0’
ADSTAT<2:0>: ADC Module Cycle Multistage Status bits⁽¹⁾
111 = ADC module is in 2^nd conversion stage
110 = ADC module is in 2^nd acquisition stage
101 = ADC module is in 2^nd precharge stage
100 = Not used
011 = ADC module is in 1^st conversion stage
010 = ADC module is in 1^st acquisition stage
001 = ADC module is in 1^st precharge stage
000 = ADC module is not converting
Note 1: If ADCS = 1, and FOSC<FRC, these bits may be invalid.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 447