PIC18LF24K Datasheet, PDF (146/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 11-5: NVMDAT: DATA EEPROM MEMORY DATA
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NVMDAT<7:0>
bit 7
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
Legend:
R = Readable bit
x = Bit is unknown
-n = Value at POR
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
bit 7-0
NVMDAT<7:0>: The value of the data memory word returned from NVMADR after a Read command,
or the data written by a Write command.
TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NVMCON1
NVMREG<1:0>
—
FREE
WRERR
WREN
WR
RD
NVMCON2
Unlock Pattern
NVMADRL
NVMADR<7:0>
NVMADRH⁽¹⁾
—
—
—
—
—
—
NVMADR<9:8>
NVMDAT
NVMDAT<7:0>
TBLPTRU
—
—
Program Memory Table Pointer (TBLPTR<21:16>)
TBLPTRH
Program Memory Table Pointer (TBLPTR<15:8>)
TBLPTRL
Program Memory Table Pointer (TBLPTR<7:0>)
TABLAT
TABLAT
INTCON
GIE/GIEH PEIE/GIEL IPEN
—
—
INT2EDG INT1EDG INT0EDG
PIE7
SCANIE CRCIE
NVMIE
—
—
—
—
CWG1IE
PIR7
SCANIF CRCIF
NVMIF
—
—
—
—
CWG1IF
IPR7
SCANIP CRCIP
NVMIP
—
—
—
—
CWG1IP
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access.
*Page provides register information.
Note 1: The NVMADRH register is not implemented on PIC18(L)F26/45/46K40.
Register
on Page
144
145
145
145
146
126*
126*
126*
125*
169
185
177
193
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 146