PIC18LF24K Datasheet, PDF (504/594 Pages) –

PIC18(L)F26/45/46K40
LFSR
Load FSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Decode
LFSR f, k
0f2
0  k  4095
k  FSRf
None
1110
1111
1110 00ff k₁₁kkk
0000 k₇kkk kkkk
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
2
2
Q2
Read literal
‘k’ MSB
Read literal
‘k’ LSB
Q3
Process
Data
Process
Data
Q4
Write
literal ‘k’
MSB to
FSRfH
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
= 03h
= ABh
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Move f
MOVF f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
f  dest
N, Z
0101 00da ffff ffff
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See Sec-
tion 35.2.3 “Byte-Oriented and Bit-
Oriented Instructions in Indexed Lit-
eral Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write W
Example:
MOVF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
REG, 0, 0
22h
FFh
22h
22h
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 504