PIC18LF24K Datasheet, PDF (261/594 Pages) –

FIGURE 20-11: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM
MODE
TMRx_clk
PRx
Instruction⁽¹⁾
ON
TMRx_ers
TMRx
TMRx_postscaled
BS F
0
0b1110
5
BS F
12345
0
1
0
12345
0
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
Rev. 10-000 202A
12/20/201 3