PIC18LF24K Datasheet, PDF (236/594 Pages) –

PIC18(L)F26/45/46K40
19.8.2
TIMER1/3/5 GATE SOURCE
SELECTION
The gate source for Timer1/3/5 can be selected using
the GSS<3:0> bits of the TMRxGATE register
(Register 19-4). The polarity selection for the gate
source is controlled by the TxGPOL bit of the TxGCON
register (Register 19-2).
Any of the above mentioned signals can be used to
trigger the gate. The output of the CMPx can be
synchronized to the Timer1/3/5 clock or left
asynchronous. For more information see Section
32.5.1 “Comparator Output Synchronization”.
19.8.3 TIMER1/3/5 GATE TOGGLE MODE
When Timer1/3/5 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1/3/5 gate signal, as opposed to the duration of a
single level pulse.
The Timer1/3/5 gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 19-5 for timing details.
Timer1/3/5 Gate Toggle mode is enabled by setting the
GTM bit of the TxGCON register. When the GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
19.8.4
TIMER1/3/5 GATE SINGLE-PULSE
MODE
When Timer1/3/5 Gate Single-Pulse mode is enabled,
it is possible to capture a single-pulse gate event.
Timer1/3/5 Gate Single-Pulse mode is first enabled by
setting the GSPM bit in the TxGCON register. Next, the
GGO/DONE bit in the TxGCON register must be set.
The Timer1/3/5 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the GGO/DONE bit will automatically be cleared.
No other gate events will be allowed to increment
Timer1/3/5 until the GGO/DONE bit is once again set in
software.
Clearing the TxGSPM bit of the TxGCON register will
also clear the GGO/DONE bit. See Figure 19-6 for tim-
ing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1/3/5
gate source to be measured. See Figure 19-7 for timing
details.
19.8.5 TIMER1/3/5 GATE VALUE STATUS
When Timer1/3/5 Gate Value Status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the GVAL bit in the
TxGCON register. The GVAL bit is valid even when the
Timer1/3/5 gate is not enabled (GE bit is cleared).
19.8.6
TIMER1/3/5 GATE EVENT
INTERRUPT
When Timer1/3/5 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of GVAL occurs,
the TMRxGIF flag bit in the PIR5 register will be set. If
the TMRxGIE bit in the PIE5 register is set, then an
interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer1/3/5 gate is not enabled (GE bit is cleared).
For more information on selecting high or low priority
status for the Timer1/3/5 Gate Event Interrupt see Sec-
tion 14.0 “Interrupts”.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 236