PIC18LF24K Datasheet, PDF (78/594 Pages) –

PIC18(L)F26/45/46K40
8.5 Low-Power Brown-out Reset
(LPBOR)
The Low-Power Brown-out Reset (LPBOR) provides
an additional BOR circuit for low power operation.
Refer to Figure 8-2 to see how the BOR interacts with
other modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset.
8.5.1 ENABLING LPBOR
The LPBOR is controlled by the LPBOREN bit of
Configuration Word 2L. When the device is erased, the
LPBOR module defaults to disabled.
8.5.1.1 LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal, which goes
to the PCON0 register and to the power control block.
8.6 MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 8-2). The RMCLR bit in the
PCON0 register will be set to ‘0’ if a MCLR has
occurred.
TABLE 8-2:
MCLRE
x
1
0
MCLR CONFIGURATION
LVP
MCLR
1
Enabled
0
Enabled
0
Disabled
8.6.1 MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
An internal Reset event (RESET, instr,
BOR, WWDT, POR STK), does not drive
the MCLR pin low.
8.6.2 MCLR DISABLED
When MCLR is disabled, the MCLR becomes
input-only and pin functions such as internal weak
pull-ups are under software control. See Section 15.1
“I/O Priorities” for more information.
8.7 Windowed Watchdog Timer
(WWDT) Reset
The Windowed Watchdog Timer generates a Reset if
the firmware does not issue a CLRWDT instruction
within the time-out period or window set. The TO and
PD bits in the STATUS register and the RWDT bit in the
PCON0 register are changed to indicate a WDT Reset.
The WDTWV bit in the PCON0 register indicates if the
WDT Reset has occurred due to a time out or a window
violation. See Section 9.0 “Windowed Watchdog
Timer (WWDT)” for more information.
8.8 RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON0 register will be set to ‘0’. See Table 8-3
for default conditions after a RESET instruction has
occurred.
8.9 Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the
PCON0 register indicate the Reset condition. These
Resets are enabled by setting the STVREN bit in
Configuration Words. See Section 10.2.1 “Stack
Overflow and Underflow Resets” for more information.
8.10 Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
8.11 Power-up Timer (PWRT)
The Power-up Timer provides a nominal 66 ms (2048
cycles of LFINTOSC) time out on POR or Brown-out
Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00000607).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 78