PIC18LF24K Datasheet, PDF (190/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 14-22: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
TMR6IP
TMR5IP
TMR4IP
TMR3IP
bit 7
R/W-1/1
TMR2IP
R/W-1/1
TMR1IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR6IP: TMR6 to PR6 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR5IP: TMR5 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 190